The invention described herein relates to semiconductor memories and more particularly to non-volatile, electrically alterable semiconductor memory cells.
Non-volatile, electrically alterable semiconductor memory cells have been developed to avoid use of semiconductor, mask programmable, read only memories and semiconductor, fusible link programmable, read only memories which, in general, are expensive and not reprogrammable. Some of the electrically alterable, semiconductor memory cells in the prior art rely on charge storage associated with a dielectric means used in a field effect transistor such as occurs in MNOS field effect transistors. Another electrically alterable semiconductor memory cell is based on a field effect transistor with a floating or electrically isolated gate wherein charge is stored on the floating gate after flowing through the insulating material surrounding the floating gate. The charge is provided on the floating gate is causing an avalanche breakdown of the semiconductor junction between the drain and the substrate of the field effect transistor of which the floating gate is part. The avalanche breakdown produces hot electrons, in a p-channel device, which are injected into the insulating material and flow to be trapped by the floating gate.
A memory cell circuit associated with this latter type of non-volatile, electrically alterable, i.e. semiconductor memory cell in monolithic integrated circuit form is shown in FIG. 1 where p-channel active devices are used, the field effect transistors, and the integrated circuit substrate, 9, is grounded. A floating gate field effect transistor, 10, has the source thereof, 14, grounded. The floating gate is designated by the numeral 11. The erasure gate, 12, for removing a bit written into the memory on transistor 10 is connected to the ERASE line. The drain thereof, 13, is connected to the source, 18, of the cell select or cell control p-channel MOS field effect transistor, 15. The drain, 17, of this latter transistor is connected to the "Y" writing/bit sensing line. The gate, 16, of the memory cell select transistor is connected to the "X" memory cell select or word select line, 20.
In operation, to write or program a bit into the memory cell, a negative voltage must be applied to the drain of the floating gate transistor 10 sufficient to cause an avalanche breakdown of the semiconductor or p-n junction occurring between the drain 13 and substrate 9. This is accomplished by applying a negative voltage to the Y line, typically in excess of 30 volts, a negative voltage to the X line of a value even more negative than that applied to the Y line, that is, more negative than the voltage value applied to the Y line by at least the threshold voltage of MOS transistor 15.
To read the cell, i.e. to sense whether the transistor 10 is in an "on" condition or an "off" condition, a substantial negative voltage is again applied to the Y line through a load, though less than that used in the writing operation. Also, a substantial negative voltage is applied to the X line. If a substantial charge has been accumulated on the floating gate 11 during a writing operation, both the floating gate transistor 10 and the select transistor 15 will be in the "on" condition when the X line voltage is applied. Otherwise, the floating gate transistor 10 will be in the "off" condition. The existing condition of the floating gate transistor 10 can be determined by the resulting voltage on the Y line.
A substantial difficulty with the circuit of FIG. 1 is the need for a large negative voltage to be applied to both the X and Y lines in operation. Large voltages in the metallization interconnection system in a monolithic integrated circuit chip lead to "channelling" problems and to dielectric breakdown problems. The likelihood of such problems is substantial where the particular metallization interconnection to which the high voltage is applied is routed over large portions of the monolithic integrated circuit as is the situation for the X and Y lines in a semiconductor memory chip.
Therefore, special design measures are required in routing the X and Y lines on such a monolithic integrated circuit chip and in the structure supporting these lines if these problems are to be avoided. Such design constraints in a monolithic integrated circuit chip could be substantially eased if the operating voltage used on one of these lines could be substantially reduced.